1. Field of the Invention
The present invention relates to a fast reading, low consumption memory device and to a reading method thereof. The invention is particularly suited for phase change memories (PCM), although it may be advantageously exploited for other kinds of memories as well.
2. Description of the Related Art
As is known, phase change memory elements exploit the characteristics of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous phase, which is disorderly, to a crystalline or polycrystalline phase, which is orderly, and the two phases are associated to considerably different resistivities.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5), which is currently widely used for storing information in overwritable disks.
In chalcogenides, the resistivity varies by two or more magnitude orders when the material passes from the amorphous phase (more resistive) to the polycrystalline phase (more conductive) and vice versa.
The use of PCM elements for forming memory cells and arrays has already been proposed. In particular, in phase change memories, a thin film of chalcogenic material is employed as a programmable resistor, which can be electrically heated by a controlled current so as to be switched between a high and a low resistance condition. The state of the chalcogenic material may be read applying a sufficiently small voltage so as not to cause a sensible heating and measuring the current passing through it. Since the current is proportional to the conductance of the chalcogenic material, it is possible to discriminate between the two states.
Regarding phase change memories reading, one of the problems to deal with is to prevent too high voltages from being accidentally applied either to selected or to unselected PCM cells of a memory array, even during transients. High voltages, in fact, may cause undesired phase transitions of some PCM cells and loss of information stored therein. In order to prevent high voltages and noise caused by adjacent memory cells, each PCM cell is generally associated to a selection element, normally a PNP bipolar transistor. In this case, each PCM cell is connected between a respective bit line and the emitter terminal of the PNP bipolar transistor forming the respective selection element. The selection element is turned on when the corresponding PCM cell is to be read and is turned off otherwise. In particular, if the selection element is a PNP bipolar transistor, a PCM cell is selected by grounding the base terminal of the corresponding selection element and by biasing the corresponding bit line at a regulated reference voltage; on the contrary, the voltage on the base terminal of a selection element is raised, and the corresponding bit line is left floating or driven to a relatively lower voltage, in order to turn off the selection element and to deselect the corresponding PCM cell.
However, leakage currents flow through cut-off selection elements and tend to charge parasitic capacitances usually associated to the bit lines of the memory array. Furthermore, leakage currents are even greater in the case a column decoder associated to the PCM memory array comprises a bit line driver stage using natural transistors as bit line voltage regulating elements. More precisely, in known memory devices, the bit line voltage regulating elements are transistors receiving a reference voltage on their control terminals and having different conductivity with respect to the decoding transistors (normally, NMOS transistors instead of PMOS transistors); natural transistors are preferred and often required to meet low supply voltage requirements, which are becoming more and more important. In order to avoid dangerous voltages, the bit lines of the whole memory array or at least the bit lines of an addressed sector of the memory array must be fully discharged before reading. In fact, the selecting elements maintain one terminal of the selected PCM cell at around the ground voltage during reading, whereas the other terminal is at the voltage of the corresponding bit line. However, the voltage on the deselected bit lines is rather high, on account of the leakage currents, so that selecting a PCM cell without discharging the corresponding bit line could easily cause undesired phase transitions.
The need for fully discharging the bit lines is clearly disadvantageous. On the one hand, in fact, repeatedly charging and discharging the bit lines lead to increased power consumption; on the other hand, reading operation is slow, since a complete discharge transient has to expire before the memory array may be properly biased. Another problem of the known memory devices is caused by the bit line voltage regulating elements. Even in the case that the bit line voltage regulating elements comprise standard transistors, in fact, their threshold voltages are sensitive to temperature variations. In other words, the bias voltage provided to the bit lines may be unstable under certain conditions.
Similar drawbacks affect also other kinds of memory devices, such as ferroelectric memories, wherein supplying too high voltages is critical and may lead either to loss of information or to reading errors.